Embodiments of the present disclosure relate to a display drive technology, and in particular, relate to a shift register unit, a gate drive circuit, and a display apparatus.
In the display drive technology, scan lines and data lines cross each other to form an active matrix. The drive circuits for the scan lines are usually realized by shift registers. The shift registers can be categorized into dynamic shift registers and static shift registers. The structure of a dynamic shift register is relatively simple, which needs small amount of Thin Film Transistor (TFT) devices; however, the power consumption of the dynamic shift register is relatively large, and its operation bandwidth is limited. The static shift register requires more TFT devices, but its operation bandwidth is large, and it costs less power. The factors, such as power consumption, reliability, and area, need to be considered together, when the performance of a shift register is considered. However, the power consumption and reliability have become important performance parameters with the size of the display panel increasing.
FIG. 1A is a schematic structure of a shift register unit in a first prior art, and FIG. 1B is an operating timing diagram of the shift register unit in the first prior art. As shown in FIG. 1A and FIG. 1B, a feedback transistor M4 connected between the output terminal and the reset drive transistor M5 is used to automatically turn off M5 in the first prior art. In particular, during a period of evaluation of the output terminal, ck1 is in high level, the output is in low level, and thus M4 is turned on, whereby M5 is turned off. During a period of reset of the output terminal, ck1 is in the low level, M3 is turned on, and in turn M5 is turned on to charge the output terminal. FIG. 2A is a schematic structure of a shift register unit in a second prior art, and FIG. 2B is an operating timing diagram of the shift register unit in the second prior art. As shown in FIG. 2A and FIG. 2B, the feedback transistor M5 is connected between the output terminal and VDD by the control of a phase-inverted clock. During a period of evaluation of the output terminal, the output becomes in low level, M5 is turned on, and M1 is turned off, which results in that the output tell final remains at the low level. During a period of reset of the output terminal, CLK becomes in low level, which turns on M3, and in turn turning on M1, whereby the output terminal is charged by VDD.
However, since the output terminal is connected with a load, its potential changes relatively slow. For the first prior art, during the period of evaluation of the output terminal, it needs time to change the output terminal from the high level to the low level, and only when the voltage of the output terminal is lower than a preset threshold voltage, M4 is turned on. Before M4 is turned on, M5 is still in ON state, therefore, there exists a direct current (DC) path from VDD to VSS though M5 and M2. For the second prior art, during the period of reset of the output terminal, it needs time to change the output terminal from the low level to the high level, so M5 is not turned off in time, therefore, there exists a direct current (DC) path from VDD to VSS though M5 and M3. The existence of the DC path results in additional transient current, and increases power consumption of the shift register.